My latest Famiclone, built-in games logic?

[mico]

I recently bought a Pegasus MT-888DX. It is a discrete chip CPU and PPU clone with built-in games (including Contra). The CPU was a TA-03NP1 and the PPU was TA-02NP and a 26.601712MHz crystal.

I posted an album here: http://imgur.com/a/b8uOn

I am in the process of doing an NTSC conversion on it,  already changed the crystal and swapped the PPU for a UMC UA6528 and the crystal for a 21.47727MHz one. Note that I have not yet swapped out the CPU, this actually works OK and many games work though there are glitches on some of the ones I've tried. There is noticeable slowdown when there are many sprites to render on the screen. I plan on hooking up the  26.601712MHz crystal oscillator to the CPU, I am in the process of building a circuit for it. I believe this would make the timing good enough to play most, if not all, games.

I also have a UMC UA6527P which lets me compare the difference in audio glitches between the two CPUs.

I am very curious about the built-in games logic, particularly how the famiclone detects that an cartridge is inserted in the game port and how it disables the built-in games. If you look at the top-side PCB pics, there is a 74LS32 above the blue cartridge port. I used a multimeter continuity check to figure out how it is all connected. Overall it makes sense but I still have one or two unresolved questions on my mind. Follow along and I'll describe the logic:

The board as Game Port 1 (P1) and Game Port 2 (P2 - built-in games). Most, but not all, pins between P1 and P2 are connected in parallel. 74LS32 is a package with 4 OR gates. The inputs to the OR gates are PPU /RD, PPU /WR or /ROMSEL from P1 and pin 46 from P1. This is the AUDIO RF pin. These are pins: 17, 44 and 47.  PPU /RD (17), /ROMSEL (44), PPU /WR (47). Finally the fourth logic gate is actually connected to the VRAM's /CS pin (VRAM 19). [note I use both VRAM and CIRAM below due to difference documentation sources).

In truth table form:

gate	A	B	Y
1	17 (PPU /RD) P1	46 (AUDIO OUT) P1	17 (PPU /RD) P2
2	47 (PPU /WR) P1	46 (AUDIO OUT) P1	47 (PPU /WR) P2
3	48 (CIRAM /CE) P2	46 (AUDIO OUT) P1	19 (CIRAM /CE) VRAM
4	44 (/ROMSEL) P1	46 (AUDIO OUT) P1	44 (/ROMSEL) P2

A few more things to note: Pin 48 on Port 1 is tied to ground, and I believe Pin 45 is held high (I have traced it back to a resistor and possibly transistor). None of these pins are connected in parallel between P1 and P2.

Finally, I think I understand how the feature works: the buillt-in cartridge is forced to be disabled when a cartridge is inserted in P1 by way of bridging Audio In to Audio RF and into the OR and results in a steady high signal, the signal is fed to the built-in cartridge which now has all of it's chips unselected. But I'm left with a few questions that I can't resolve:

1. I assume this means games that use audio expansion would not work on this famiclone, at least no the extra sound channels.
2. I don't understand why P1 pin 48 (CIRAM /CE) is tied to ground. How does the VRAM /CS logic work then. Is it always enabled when a cartridge is inserted? Don't games select it in and out on demand?


Post Merge: February 01, 2016, 07:25:04 pm
A self reply is better than no reply. I'm studying documentation until I reach enlightenment...

1. I assume this means games that use audio expansion would not work on this famiclone, at least no the extra sound channels.

That's a safe assumption...

2. I don't understand why P1 pin 48 (CIRAM /CE) is tied to ground. How does the VRAM /CS logic work then. Is it always enabled when a cartridge is inserted? Don't games select it in and out on demand?

I gather that /A13 is usually mapped CIRAM /CE. Most games don't touch CIRAM /CE directly and the address banks just split naturally between cart and CIRAM (which I called VRAM above). I am very curious to know if Gauntlet or Rad Racer II work on my famiclone. I'm guessing they do not, I googled around and it seems that they commonly fail to work on famiclones.

From http://nesdev.com/rom.txt

1) You can disable the CIRAM all together by pulling pin 57 high.  You can
then place  4K of RAM onto the bus with it's /CE tied to pin 58.  This
will place that 4K of RAM at 0000-1FFF.  Gauntlet is an example of a cart
that does this.  (The carts I've seen use a 6264 8K RAM with A12 tied
low so it's effectively 4K).

2) Horizontal / Vertical mirroring.  A10 of the CIRAM was brought out to
the cart edge for just this reason.  If you tie it to A10, you'll get
vertical mirroring; since the first two banks will be in sequence.
However, if you tie it to A11, you'll get horizontal mirroring; adjacent
twin banks will be the same.

3) The MMCs can control the A10 line of the CIRAM to change either the
screen or mirroring type on the fly. 

4) The LS161 mappers can change the state of the A10 line; however why
this would be desireable is anyone's guess. :-)

[Crissaegrim87]

Hi, I have a lot of famiclones with this type of internal slot, but I did not know they disabled features. Next time I will check all your data in the PCB to correct them and make compatible again with these features. Thanks for your work, if you wanna check my youtube channel is joaco retrotech, there I will upload the resulta